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wifi: mt76: mt7603: fix tx filter/flush function

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Setting MT_TX_ABORT does not abort any transmission for a wtbl index on its
own. Instead, it modifies the behavior of a queue flush to make it selectively
flush packets for a particular wtbl index.
Adjust powersave filtering to make use of this in order to avoid running into
unnecessary timeouts while flushing

Signed-off-by: Felix Fietkau <[email protected]>
(cherry picked from commit 7ef4dd12d9)
This commit is contained in:
Felix Fietkau
2023-08-26 15:05:17 +02:00
parent 9dda9f709c
commit 2cbd5df8cf
4 changed files with 28 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
mt7603/mac.c
+16 -5
View File
@@ -178,8 +178,9 @@ mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled)
mt76_wr(dev, addr + 3 * 4, val); mt76_wr(dev, addr + 3 * 4, val);
} }
void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort) void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort)
{ {
u32 flush_mask;
int i, port, queue; int i, port, queue;
if (abort) { if (abort) {
@@ -195,6 +196,18 @@ void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort)
mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN | mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN |
FIELD_PREP(MT_TX_ABORT_WCID, idx)); FIELD_PREP(MT_TX_ABORT_WCID, idx));
flush_mask = MT_WF_ARB_TX_FLUSH_AC0 |
MT_WF_ARB_TX_FLUSH_AC1 |
MT_WF_ARB_TX_FLUSH_AC2 |
MT_WF_ARB_TX_FLUSH_AC3;
flush_mask <<= mac_idx;
mt76_wr(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask);
mt76_poll(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask, 0, 20000);
mt76_wr(dev, MT_WF_ARB_TX_START_0, flush_mask);
mt76_wr(dev, MT_TX_ABORT, 0);
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY | mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) | FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) |
@@ -202,13 +215,11 @@ void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort)
FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) | FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) |
FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue)); FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue));
mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 15000); mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000);
} }
WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY); WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY);
mt76_wr(dev, MT_TX_ABORT, 0);
mt7603_wtbl_set_skip_tx(dev, idx, false); mt7603_wtbl_set_skip_tx(dev, idx, false);
} }
@@ -245,7 +256,7 @@ void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
if (enabled) if (enabled)
mt7603_filter_tx(dev, idx, false); mt7603_filter_tx(dev, sta->vif->idx, idx, false);
addr = mt7603_wtbl1_addr(idx); addr = mt7603_wtbl1_addr(idx);
mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
mt7603/main.c
+4 -1
View File
@@ -69,6 +69,7 @@ mt7603_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
INIT_LIST_HEAD(&mvif->sta.poll_list); INIT_LIST_HEAD(&mvif->sta.poll_list);
mvif->sta.wcid.idx = idx; mvif->sta.wcid.idx = idx;
mvif->sta.wcid.hw_key_idx = -1; mvif->sta.wcid.hw_key_idx = -1;
mvif->sta.vif = mvif;
mt76_packet_id_init(&mvif->sta.wcid); mt76_packet_id_init(&mvif->sta.wcid);
eth_broadcast_addr(bc_addr); eth_broadcast_addr(bc_addr);
@@ -357,6 +358,7 @@ mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
msta->smps = ~0; msta->smps = ~0;
msta->wcid.sta = 1; msta->wcid.sta = 1;
msta->wcid.idx = idx; msta->wcid.idx = idx;
msta->vif = mvif;
mt7603_wtbl_init(dev, idx, mvif->idx, sta->addr); mt7603_wtbl_init(dev, idx, mvif->idx, sta->addr);
mt7603_wtbl_set_ps(dev, msta, false); mt7603_wtbl_set_ps(dev, msta, false);
@@ -380,12 +382,13 @@ mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
struct ieee80211_sta *sta) struct ieee80211_sta *sta)
{ {
struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv; struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv;
spin_lock_bh(&dev->ps_lock); spin_lock_bh(&dev->ps_lock);
__skb_queue_purge(&msta->psq); __skb_queue_purge(&msta->psq);
mt7603_filter_tx(dev, wcid->idx, true); mt7603_filter_tx(dev, mvif->idx, wcid->idx, true);
spin_unlock_bh(&dev->ps_lock); spin_unlock_bh(&dev->ps_lock);
spin_lock_bh(&dev->sta_poll_lock); spin_lock_bh(&dev->sta_poll_lock);
mt7603/mt7603.h
+1 -1
View File
@@ -234,7 +234,7 @@ void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
bool enabled); bool enabled);
void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta, void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
bool enabled); bool enabled);
void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort); void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort);
int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
enum mt76_txq_id qid, struct mt76_wcid *wcid, enum mt76_txq_id qid, struct mt76_wcid *wcid,
mt7603/regs.h
+7
View File
@@ -309,6 +309,13 @@ enum {
#define MT_WF_ARB_TX_STOP_0 MT_WF_ARB(0x110) #define MT_WF_ARB_TX_STOP_0 MT_WF_ARB(0x110)
#define MT_WF_ARB_TX_STOP_1 MT_WF_ARB(0x114) #define MT_WF_ARB_TX_STOP_1 MT_WF_ARB(0x114)
#define MT_WF_ARB_TX_FLUSH_AC0 BIT(0)
#define MT_WF_ARB_TX_FLUSH_AC1 BIT(5)
#define MT_WF_ARB_TX_FLUSH_AC2 BIT(10)
#define MT_WF_ARB_TX_FLUSH_AC3 BIT(16)
#define MT_WF_ARB_TX_FLUSH_AC4 BIT(21)
#define MT_WF_ARB_TX_FLUSH_AC5 BIT(26)
#define MT_WF_ARB_BCN_START MT_WF_ARB(0x118) #define MT_WF_ARB_BCN_START MT_WF_ARB(0x118)
#define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n)) #define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n))
#define MT_WF_ARB_BCN_START_T_PRE_TTTT BIT(10) #define MT_WF_ARB_BCN_START_T_PRE_TTTT BIT(10)