diff --git a/mt7603_init.c b/mt7603_init.c
index 61d7aedf..3750c462 100644
--- a/mt7603_init.c
+++ b/mt7603_init.c
@@ -58,6 +58,8 @@ mt7603_set_tmac_template(struct mt7603_dev *dev)
 static int
 mt7603_mac_reset(struct mt7603_dev *dev)
 {
+	u32 addr;
+
 	mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);
 
 	/* Disable MAC */
@@ -65,8 +67,7 @@ mt7603_mac_reset(struct mt7603_dev *dev)
 	mt76_wr(dev, MT_WF_ARB_TQCR0, 0);
 	mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
 
-	mt76_rmw(dev, MT_DMA_DCR0, 0xffff, 0xc0211000);
-	mt76_wr(dev, MT_DMA_DCR1, GENMASK(13, 11));
+	mt76_rmw(dev, MT_DMA_DCR0, ~0xfffc, 0x400);
 
 	mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));
 	mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));
@@ -80,6 +81,16 @@ mt7603_mac_reset(struct mt7603_dev *dev)
 
 	mt7603_set_tmac_template(dev);
 
+	/* Enable RX group to HIF */
+	addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
+	mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS);
+
+	/* Enable RX group to MCU */
+	mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));
+
+	/* Configure all rx packets to HIF */
+	mt76_wr(dev, MT_DMA_RCFR0, 0xc0200000);
+
 	return 0;
 }
 
diff --git a/mt7603_regs.h b/mt7603_regs.h
index 708ba4a0..8720f332 100644
--- a/mt7603_regs.h
+++ b/mt7603_regs.h
@@ -227,6 +227,9 @@
 
 #define MT_CLIENT_TMAC_INFO_TEMPLATE	0x040
 
+#define MT_CLIENT_RXINF			0x068
+#define MT_CLIENT_RXINF_RXSH_GROUPS	GENMASK(2, 0)
+
 #define MT_PSE_BASE_PHYS_ADDR		0xa0000000
 
 #define MT_PSE_WTBL_2_PHYS_ADDR		0xa5000000