diff --git a/mt7603_init.c b/mt7603_init.c
index a98206b4..b13bdf09 100644
--- a/mt7603_init.c
+++ b/mt7603_init.c
@@ -68,14 +68,14 @@ mt7603_mac_reset(struct mt7603_dev *dev)
 	mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);
 	mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
 
-	mt76_rmw(dev, MT_DMA_DCR0, ~0xfffc, 0x400);
+	mt76_rmw(dev, MT_DMA_DCR0, ~0xfffc, MT_RX_BUF_SIZE);
 
 	mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));
 	mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));
 
 	mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31));
 
-	mt76_set(dev, MT_WF_RMAC_RMACDR, BIT(30));
+	mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT);
 	mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);
 
 	mt76_wr(dev, MT_WF_RFCR1, 0);
@@ -209,6 +209,9 @@ mt7603_mac_init(struct mt7603_dev *dev)
 
 	eth_broadcast_addr(addr);
 	mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, addr);
+
+	mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2);
+	mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2);
 }
 
 static int
diff --git a/mt7603_regs.h b/mt7603_regs.h
index a766dd42..cf472598 100644
--- a/mt7603_regs.h
+++ b/mt7603_regs.h
@@ -208,7 +208,12 @@
 #define MT_WF_RFCR_DROP_NDPA		BIT(20)
 #define MT_WF_RFCR_DROP_UNWANTED_CTL	BIT(21)
 
-#define MT_WF_RMAC_RMACDR		MT_WF_RMAC(0x078)
+#define MT_WF_RMACDR			MT_WF_RMAC(0x078)
+#define MT_WF_RMACDR_TSF_PROBERSP_DIS	BIT(0)
+#define MT_WF_RMACDR_TSF_TIM		BIT(4)
+#define MT_WF_RMACDR_MBSSID_MASK	GENMASK(25, 24)
+#define MT_WF_RMACDR_CHECK_HTC_BY_RATE	BIT(26)
+#define MT_WF_RMACDR_MAXLEN_20BIT	BIT(30)
 
 #define MT_WF_RMAC_RMCR			MT_WF_RMAC(0x080)
 #define MT_WF_RMAC_RMCR_SMPS_MODE	GENMASK(21, 20)
@@ -234,6 +239,12 @@
 
 #define MT_WTBL_RMVTCR			MT_WTBL_OFF(0x008)
 
+#define MT_LPON_BASE			0x24000
+#define MT_LPON(n)			(MT_LPON_BASE + (n))
+
+#define MT_LPON_BTEIR			MT_LPON(0x020)
+#define MT_LPON_BTEIR_MBSS_MODE		GENMASK(31, 29)
+
 #define MT_WTBL1_BASE			0x28000
 
 #define MT_PCIE_REMAP_BASE_1		0x40000