diff --git a/mt7603.h b/mt7603.h index 4658d33b..efb7c0a8 100644 --- a/mt7603.h +++ b/mt7603.h @@ -99,6 +99,7 @@ struct mt7603_dev { u8 rssi_offset[3]; + u8 slottime; s16 coverage_class; struct mt7603_mcu mcu; diff --git a/mt7603_init.c b/mt7603_init.c index 23d80005..5c11df77 100644 --- a/mt7603_init.c +++ b/mt7603_init.c @@ -327,6 +327,7 @@ int mt7603_register_device(struct mt7603_dev *dev) dev->rx_chains = 2; dev->tx_chains = 2; + dev->slottime = 9; ret = mt7603_init_hardware(dev); if (ret) diff --git a/mt7603_mac.c b/mt7603_mac.c index 6fb9342e..a611850d 100644 --- a/mt7603_mac.c +++ b/mt7603_mac.c @@ -50,9 +50,24 @@ void mt7603_mac_set_timing(struct mt7603_dev *dev) int offset = 3 * dev->coverage_class; u32 reg_offset = MT76_SET(MT_TIMEOUT_VAL_PLCP, offset) | MT76_SET(MT_TIMEOUT_VAL_CCA, offset); + int sifs; + u32 val; + + if (dev->chandef.chan->band == IEEE80211_BAND_5GHZ) + sifs = 16; + else + sifs = 10; + + mt7603_mac_stop(dev); mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); + val = MT76_SET(MT_IFS_EIFS, 360) | + MT76_SET(MT_IFS_RIFS, 2) | + MT76_SET(MT_IFS_SIFS, sifs) | + MT76_SET(MT_IFS_SLOT, dev->slottime); + + mt7603_mac_start(dev); } static void diff --git a/mt7603_main.c b/mt7603_main.c index 21fe71b5..ac3aa0c8 100644 --- a/mt7603_main.c +++ b/mt7603_main.c @@ -145,6 +145,7 @@ mt7603_config(struct ieee80211_hw *hw, u32 changed) if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { ret = mt7603_set_channel(dev, &hw->conf.chandef); + mt7603_mac_set_timing(dev); } mutex_unlock(&dev->mutex); @@ -197,6 +198,12 @@ static void mt7603_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_bss_conf *info, u32 changed) { + struct mt7603_dev *dev = hw->priv; + + if (changed & BSS_CHANGED_ERP_SLOT) { + dev->slottime = info->use_short_slot ? 9 : 20; + mt7603_mac_set_timing(dev); + } } static int diff --git a/mt7603_regs.h b/mt7603_regs.h index 338526bd..e3a19a48 100644 --- a/mt7603_regs.h +++ b/mt7603_regs.h @@ -222,6 +222,12 @@ #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) +#define MT_IFS MT_WF_TMAC(0x0a4) +#define MT_IFS_EIFS GENMASK(8, 0) +#define MT_IFS_RIFS GENMASK(14, 10) +#define MT_IFS_SIFS GENMASK(22, 16) +#define MT_IFS_SLOT GENMASK(30, 24) + #define MT_WF_RMAC_BASE 0x21800 #define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs))